Beyond Moore’s Law: Why Chipmakers Are Stacking Silicon Up

For five decades, a faster chip meant a smaller transistor. That trade has quietly stopped paying off, and the search for performance beyond Moore’s Law is no longer about shrinking circuits sideways. It is about stacking them upward, one layer of silicon on top of another. The cost of each new manufacturing node has climbed, the physics has turned hostile, and the price of a single transistor, which fell for forty years, started rising again more than a decade ago.

So the number you have been trained to watch, 3 nanometers, then 2, matters less than the industry now lets on. The harder question is how chipmakers connect silicon vertically once they can no longer pack more in flat. A paper published in Nature on 28 May 2026 by a team at the University of Illinois Urbana-Champaign suggests the method for doing that may be about to change.

Why Shrinking Stopped Paying Off

Moore’s Law was always two things at once: a physics observation and an economics promise. The physics said you could fit twice as many transistors in the same space every couple of years. The economics said each of those transistors would get cheaper. The first is still roughly true. The second broke years ago.

Cost per transistor stopped falling around 2011 at the 28-nanometer node. Since then it has climbed, reaching about $2.16 at today’s leading 3-nanometer process, a level last seen near 2005. A single leading-edge fabrication plant now runs past $20 billion to build. The industry kept transistor density rising through extreme ultraviolet (EUV) lithography and gate-all-around (GAA) transistor structures, but it bought that density at sharply higher cost and complexity.

The physical wall is just as real. As transistors approach atomic scale, electrical leakage rises, heat gets harder to shed, and the precision needed to print features climbs. Qing Cao, an associate professor of materials science and engineering at Illinois who led the new research, puts the ceiling plainly. “In a sense, we’re hitting a limit imposed by physics,” he said. “If you look at the actual size of transistors, they’re not getting smaller, especially in terms of their contacted gate pitch.”

• $2.16 per transistor at the 3nm node, up from the 2011 floor
• 2011 / 28nm the point where cost per transistor stopped falling
• $20 billion+ the price of a single new leading-edge fab

When the gate pitch stalls and every new node costs more per switch, the old playbook stops working. That is the moment the field started looking up instead of in.

The Routes Chipmakers Are Taking Now

There is no single replacement for shrinking. Instead, the industry has split into several directions, each suited to a different problem. Three of them are already in production or near it, and a fourth, the one the Illinois team is chasing, is still in the lab.

One route is to make the chip enormous. Wafer-scale engines (WSE, a single processor carved from an entire silicon wafer) avoid stitching many chips together. Cerebras Systems builds these for artificial intelligence training; its latest design packs roughly 4 trillion transistors and 900,000 cores onto one wafer, with on-chip memory bandwidth that dwarfs a conventional graphics processor. The catch is that the parts are costly, hard to manufacture, and built only for heavy AI work, not phones or laptops.

The other two production routes both stack, but differently. Taiwan Semiconductor Manufacturing Company bonds whole wafers together in its wafer-on-wafer (WoW) process, shortening the distance data travels; its SoW-X platform promises around 40 times the compute of current packaging, with volume production targeted for 2027. Intel’s Foveros takes a more modular path, stacking smaller dies, or chiplets, on a base die so each piece can be built on a different node. You can read more on how TSMC and Intel are scaling advanced packaging as the two compete for the same customers.

Where Today’s 3D Stacking Hits a Wall

For all their differences, the production methods share one constraint. They stack layers that were manufactured separately, then connect them after the fact. Those vertical links, added once each layer already exists, are far sparser than the wiring inside a single sheet of silicon.

That gap matters more as workloads get hungrier. In a memory-heavy AI job, the bottleneck is no longer how fast a core computes but how fast data moves between layers. Bonded designs help, yet they cannot match the connection density you get within one continuous plane of circuitry. So the prize everyone is circling is a chip whose layers are built together, not glued together.

The Illinois Method, Built Layer by Layer

That is the target of monolithic 3D integration, where circuits are grown directly on top of one another rather than bonded as finished tiers. Done right, the vertical connections between layers approach the density of the wiring inside a single layer. The reason it has stayed in the lab for years comes down to one number: temperature.

The Heat Problem That Blocked True 3D

Conventional silicon fabrication needs heat as high as 1,000 degrees Celsius. Apply that to a finished bottom layer while building the next one and you cook the circuits underneath. That single constraint, the thermal budget, is what kept true layer-by-layer silicon impractical. The Illinois group says it has met that budget for the first time using standard single-crystalline silicon.

For the first time, we have met the thermal budget of monolithic 3D integration using standard single-crystalline silicon and delivered unprecedented performance.

That line came from Qing Cao, describing the team’s result in the university’s announcement of the Nature work. The emphasis on standard silicon is the point. A process that plugs into existing foundry lines has a far shorter road to a real product than one built on exotic materials.

Rolling On Sheets of Ten-Nanometer Silicon

The method uses ultra-thin silicon sheets, around 10 nanometers thick, peeled from a specialized substrate and rolled onto the wafer at temperatures below 200 degrees Celsius. Because the sheets are so thin, they can be transferred and processed without the high heat that would damage the layers already in place. The team aligned those layers to better than 10-nanometer accuracy and separated them with roughly 90 nanometers of dielectric.

Junctionless Transistors Keep the Process Cool

The second trick is the transistor itself. Instead of conventional devices with p-n junctions, the team used junctionless transistors, where the silicon is uniformly and heavily doped before stacking begins. That avoids the high-temperature steps junctions normally require. In their demonstration, the researchers stacked three layers of 625 transistors each and recorded device yields of 98 to 100 percent, with current densities they report as three to four times greater than competing monolithic materials. A six-transistor memory cell, the basic building block of on-chip static random-access memory (SRAM, the fast memory built into CPUs and GPUs), shrank to about one-third the footprint of its flat layout. The full results sit in the team’s peer-reviewed paper on monolithic three-dimensional silicon integration.

Who Stands to Gain From a Vertical Turn

The obvious winners are the workloads that choke on data movement. AI training and high-performance computing (HPC, the large clustered systems behind weather models and scientific simulation) spend more energy shuttling bits than crunching them, and denser vertical links attack exactly that cost. The less obvious beneficiaries are scattered across the supply chain.

• Memory designers, because spreading an SRAM cell across layers cuts the area that fast on-chip memory eats today
• Foundries, since a silicon-based, foundry-compatible process can ride existing tools rather than demand a new line
• System builders in phones and laptops, where vertical density buys performance without a larger footprint

The funding map already hints at industry interest. The Illinois work was backed by the National Science Foundation and the Silicon Crossroads Microelectronics Commons Hub, with IBM, Intel and TSMC listed among the industry partners. That mix matters in a field where chip controls have grown political; the same firms navigating tightened export rules, including the latest US restrictions on advanced AI chip sales, are the ones funding the next architecture.

What Still Has to Be Proven

Three working layers in a lab is a long way from a shipping product. The team argues the stack can grow taller. “You can keep stacking layers beyond the three we demonstrated,” Cao said. “And the process will yield high-performing transistors with high yield and low variability.” That claim is the one a foundry will test first.

The harder proof is manufacturing at volume. A near-perfect yield across 625 transistors per layer does not guarantee the same across billions, and the researchers themselves want to refine the process inside a commercial foundry before declaring victory. Cost, throughput, and how the thermal budget holds up across many more layers all remain open. For a fuller picture of where the broader scaling debate stands, imec’s assessment of whether Moore’s Law has actually run out lays out the competing views.

If the Illinois method survives the jump from wafer to fab, the chips in data centers, and eventually in consumer devices, start being judged by how many layers they stack rather than how small their features are. If it stalls in the transfer to manufacturing, the field falls back on bonded wafers and chiplets, and the vertical promise waits for the next group to crack the thermal budget.

Frequently Asked Questions

What does going beyond Moore’s Law actually mean?

It means finding performance gains that no longer come from shrinking transistors. As nodes reach a few nanometers, the cost per transistor rises and the physics gets harder, so chipmakers turn to vertical stacking, wafer-scale designs, and chiplets to keep computing power climbing.

What is monolithic 3D integration?

Monolithic 3D integration builds circuit layers directly on top of one another during manufacturing, rather than bonding separately made chips together afterward. Because the layers are formed in place, the vertical connections between them can be far denser than in bonded designs, which speeds up data movement.

How is it different from TSMC’s wafer-on-wafer or Intel’s Foveros?

Wafer-on-wafer bonds whole finished wafers, and Foveros stacks separate finished dies, or chiplets, on a base die. Both connect layers after each is made. Monolithic 3D grows the layers together, so its interlayer links approach the density of wiring inside a single sheet of silicon.

Why was temperature the main obstacle to 3D silicon chips?

Standard silicon fabrication needs heat up to 1,000 degrees Celsius. Applying that while building an upper layer would damage the circuits already below it. The Illinois team works at less than 200 degrees Celsius by using ultra-thin silicon sheets and junctionless transistors, protecting the lower layers.

When could this technology reach real products?

No firm date exists. The research demonstrated three stacked layers in a lab with 98 to 100 percent device yield, and the team wants to refine the process inside a commercial foundry before scaling. Industry partners include IBM, Intel and TSMC, but volume manufacturing has not been announced.

Will this make consumer phones and laptops faster?

Potentially, yes. Denser vertical integration can deliver more performance in the same footprint, which suits compact devices. The earliest impact, though, is expected in AI and high-performance computing, where the cost of moving data between layers is the biggest bottleneck.