Illinois 3D Silicon Stack Could Stretch Moore’s Law for Years

A team at the University of Illinois Urbana-Champaign has stacked three working layers of single-crystal silicon directly on top of one another at temperatures below 200 degrees Celsius, a monolithic 3D integration method that could keep Moore’s law moving after transistor shrinking runs out of room. The work, published in the journal Nature’s electronic-devices research, reports device yields of 98 to 100% using the same silicon that runs every modern processor.

The first place that math pays off is on-chip memory, the dense cache that stopped shrinking years ago and now throttles artificial-intelligence accelerators. That is the part of the story most coverage skips, and it is where stacked silicon could matter before it ever touches a logic core.

How Illinois Stacked Silicon Without Cooking the Circuit

The trick is a sheet of silicon thinner than a virus. The team, led by Qing Cao, a materials science and engineering professor at Illinois Grainger College of Engineering, peels ultrathin freestanding silicon nanomembranes off a donor wafer and lays them onto a substrate that already holds finished circuitry.

A roll laminator presses each membrane down, and because the films are 10 nanometers thick or less, they bend to fit the surface below instead of fighting it. A standard wafer runs 500 to 700 micrometers thick, tens of thousands of times more, and forcing two rigid wafers together tends to trap voids at the interface. The thin membranes conform, so those defects largely vanish.

Here is the cluster of numbers that makes the demonstration credible:

• 98 to 100% working-device yield across the stacked tiers
• Three layers, each carrying 625 junctionless transistors over a 1,600-square-millimeter area
• Roughly 90 nanometers of separation between layers, with vertical alignment held to sub-10-nanometer accuracy
• Bonding done at no more than 200 degrees Celsius, half the heat competing monolithic methods need

Cao reaches for a city-planning image to explain why building up beats building out.

Take something as simple as static random-access memory, which is universal in CPUs and GPUs. Today it takes six microelectronic devices called transistors on a single plane to store one bit of information. With vertical integration, you can distribute them across multiple layers. It’s like replacing a sprawling suburb with high-rises: you get the same functionality, but the spatial footprint is reduced while making communication between layers faster and more efficient.

That quote, given in the university’s announcement, points at the real target. The example is not chosen at random.

Why Shrinking Transistors Stopped Paying Off

For about 60 years, the industry kept its promise by making transistors smaller. Moore’s law, the observation that transistor density roughly doubles every two years, held up far longer than anyone expected. It is now getting expensive and slow to keep going.

The reason is physical, not financial. Cao notes that transistors are no longer really getting smaller in the dimension that counts, the contacted gate pitch, because silicon’s material properties and the rules of quantum mechanics set a floor. Squeeze closer and electrons start leaking where they should not.

So engineers are turning the chip on its side. Stacking layers adds room for components without a smaller transistor, and it shortens the wiring between parts of the circuit. Shorter wires mean less parasitic capacitance and far more bandwidth between blocks, which is exactly what data-hungry workloads crave.

The SRAM Bottleneck Hiding Behind the Headline

Cao’s static random-access memory (SRAM, the fast cache built into every processor) example is the tell. SRAM is where the consensus shrink story already broke, and it is where a vertical fix would land first.

The Cell That Quit Shrinking

An SRAM bit cell needs six transistors to store a single bit, all laid out on one flat plane. As logic transistors kept getting denser, those cells stopped keeping pace. According to chipmaker disclosures for the 3-nanometer generation, the SRAM bit cell barely moved from the prior node, and on one variant of the process it did not shrink at all, even as logic density rose well over 1.5 times.

Why AI Chips Feel It Hardest

Modern AI accelerators pack enormous amounts of cache because moving data between memory and compute burns time and power. When SRAM refuses to scale, that cache eats a bigger and bigger share of the die, and the cost per chip climbs. Distributing those six transistors across stacked layers, as Cao describes, attacks the problem at its source rather than patching it with circuit tricks. The Illinois team built and ran SRAM cells with a footprint roughly one-third the size of their flat equivalents, which is the headline number that should interest anyone designing memory-heavy silicon.

Monolithic Stacking Versus the 3D Chips You Already Own

Three-dimensional chips are already shipping. High-bandwidth memory in AI servers and AMD’s 3D V-Cache in gaming processors both stack silicon. They do it by building devices on separate wafers and bonding the finished slabs together, connected by through-silicon vias (TSVs, the vertical wires that punch through a wafer).

Monolithic integration is a different animal. Each new device layer is grown directly on the one beneath it, so the vertical connections can be far smaller and far denser. The contrast is what makes the Illinois result matter.

That last row is the quiet win. Earlier monolithic attempts swapped in alternative materials for the top layers to dodge the heat problem, and they paid for it in performance.

Junctionless Transistors and the 400-Degree Ceiling

The wall every monolithic effort hits is temperature. Growing high-quality crystalline silicon and building fast transistors normally needs heat approaching 1,000 degrees Celsius, but once the bottom layer has metal wiring in it, anything past roughly 400 degrees melts the connections.

Dropping the Doping Heat

Conventional transistors rely on doping, adding impurities to specific regions of silicon to steer current, a step that usually demands above 600 degrees Celsius. The Illinois group sidestepped it with junctionless transistors, where the silicon is uniformly and heavily doped before any stacking begins. The films are thin enough that the gate still controls current cleanly, and the heavy doping cuts contact resistance.

Performance That Holds Up

The payoff is that the stacked devices behave like real silicon. Their output current densities matched conventional transistors built on bulk wafers at far higher temperatures, and they beat monolithic devices made from alternative materials by at least three to four times. Cao framed the broader stakes in the university’s statement.

“For the first time, we have met the thermal budget of monolithic 3D integration using standard single-crystalline silicon and delivered unprecedented performance,” he said. Sticking with mainstream silicon also means the process can drop into existing fabrication lines instead of demanding a new materials supply chain.

What Still Stands Between the Lab and a Foundry

This is a research demonstration, and the distance to a product is the part worth keeping in view. The team is preparing to hand the process to an industrial foundry, but the gap from bench to high-volume manufacturing is wide.

The Scale Gap

The demonstration ran on a 75-millimeter wafer; commercial fabs run 300-millimeter wafers. Each tier held 625 transistors, while a modern processor carries tens of billions. The junctionless devices delivered above 650 milliamperes per micrometer of current, solid for older commercial silicon, though the most advanced production transistors clear 1,000. None of that sinks the idea; it just marks how much engineering separates a proof of concept from a yielding production node.

The Partners and the Clock

The work ran through Illinois Grainger Engineering’s Center for Advanced Semiconductor Chips with Accelerated Performance, whose industry partners include IBM, Intel, and Taiwan Semiconductor Manufacturing Company, with funding from the National Science Foundation’s research programs and the Silicon Crossroads Microelectronics Commons Hub. Cao began the research in 2019 and says the fundamental barriers fell in 2024, which puts a realistic clock on commercialization that is measured in years, not quarters. More on the group’s work sits on the Illinois materials science faculty page for Qing Cao.

Cao argues the decisive result is scalability, the ability to keep adding layers past the three shown while holding yield and low variability. If that holds at a foundry, the SRAM-heavy AI chips straining against the memory wall are the first customers who get relief. If it stalls at scale, the demonstration stays an elegant paper while the industry keeps patching flat cache with circuit tricks, and the reprieve for Moore’s law arrives later than the headlines suggest.

Frequently Asked Questions

What Is Monolithic 3D Integration?

Monolithic 3D integration builds each new layer of transistors directly on top of a finished circuit layer, rather than making layers on separate wafers and bonding them together. Because the layers are grown in place, the vertical connections between them can be far smaller and denser, potentially 10 to 100 times more connections than conventional stacking.

How Is It Different From HBM or AMD’s 3D V-Cache?

High-bandwidth memory and AMD’s 3D V-Cache stack silicon that was manufactured on separate wafers, then joined with large through-silicon vias. The Illinois monolithic method grows layers sequentially with roughly 90 nanometers between them and nanometer-scale alignment, which allows much tighter interlayer wiring than bonded approaches.

Why Does Heat Limit Stacking Chips?

Building fast silicon transistors normally needs temperatures near 1,000 degrees Celsius, but once a layer contains metal interconnects, anything above about 400 degrees Celsius destroys them. That 400-degree thermal budget is why earlier teams switched to weaker alternative materials for upper layers; the Illinois process stays under 200 degrees and keeps using single-crystal silicon.

What Are Junctionless Transistors?

Junctionless transistors are uniformly and heavily doped before fabrication, so they avoid the high-temperature doping step (above 600 degrees Celsius) that conventional transistors require. Their silicon films are thin enough that the gate still switches current cleanly, which let the team build high-performance devices within the low thermal budget.

When Could This Reach Commercial Chips?

Not soon. The work is a research demonstration on a 75-millimeter wafer with 625 transistors per layer, far from the 300-millimeter wafers and billions of transistors of production fabs. The team is preparing to transfer the process to an industrial foundry, a step that typically takes years.

Does This Really Extend Moore’s Law?

It offers a path. Moore’s law is slowing because transistors are near physical size limits, so adding density by stacking layers rather than shrinking devices is one credible way to keep computing power rising. Whether it sustains the doubling trend depends on proving the process scales reliably at a commercial foundry.